A Defect-tolerant Cluster in a Mesh SRAM-based FPGA

International audienceIn this paper, we propose the implementation of multiple defect-tolerant techniques on an SRAM-based FPGA. These techniques include redundancy at both the logic block and intra-cluster interconnect. In the logic block, redundancy is implemented at the multiplexer level. Its efficiency is analyzed by injecting a single defect at the output of a multiplexer, considering all possible locations and input combinations. While at the interconnect level, fine grain redundancy is introduced which not only bypasses defects but also increases routability. Taking advantage of the sparse intra-cluster interconnect structures, routability is further improved by efficient distribution of feedback paths allowing more flexibility in the connections among logic blocks. Emulation results show a significant improvement of about 15% and 34% in the robustness of logic block and intra-cluster interconnect respectively. Furthermore, the impact of these hardening schemes on the testability of the FPGA cluster for manufacturing defects is also investigated in terms of maximum achievable fault coverage and the respective cost

Architectures matérielles pour l'arithmétique stochastique discrète

The use of floating point arithmetic in scientific computations is a source of problems of precision. Since all real numbers cannot represented in floating-point format, some will have to be approximated. The discrete stochastic arithmetic permits to control and estimate rounding errors. The software implementation of this arithmetic suffers from computation bottlenecks. The aim of this thesis is to propose a hardware architecture to reduce this cost. First we implemented in hardware the specific functionalities of discrete stochastic arithmetic which are the random rounding mode, the computation of the number of significant bits, the detection of informatical zeroes and the control of the operations of comparison. Second, since the discrete stochastic arithmetic is based on floating-point arithmetic, we developed a floating-point unit. The specific hardware, need for the control and the estimation of round-off errors propagation, was added. Thus a floating-point unit computing the operations of addition, subtraction, multiplication, division, comparison and conversions, with estimation and control of the round-off errors, was developed to the physical layout. Finally we integrated this unit in a system on chip to be able to use it by computing programs and to compare the performances with the software.L'utilisation de l'arithmétique à virgule flottante dans le calcul scientifique pose des problèmes de précision. En effet, les nombres réels n'étant pas tous représentables en virgule flottante, certains vont devoir être approchés. L'arithmétique stochastique discrète permet d'estimer et de contrôler les arrondis de calcul. L'utilisation logicielle de cette arithmétique est très coûteuse en temps de calcul. Le but de cette thèse est donc de proposer une architecture matérielle permettant de réduire ce coût. Dans un premier temps nous avons réalisé en matériel les fonctionnalités, spécifiques à l'arithmétique stochastique discrète, que sont l'arrondi aléatoire, le calcul du nombre de chiffres significatifs, la détection des zéros informatiques et le contrôle des opérations de comparaison. Cette arithmétique s'appuyant sur l'arithmétique à virgule flottante, il a falludans un deuxième temps développer une unité de calcul sur des nombres à virgule flottante. A cette unité a été ajouté le matériel nécessaire au contrôle et à l'estimation des arrondis de calcul. Ainsi une unité de calcul en virgule flottante effectuant les opérations d'addition, soustraction, multiplication, division, comparaison et conversions, avec estimation et contrôle des arrondis de calcul, a été réalisée jusqu'au dessin des masques physiques. Enfin nous avons intégré cette unité au sein d'un système sur puce afin de pouvoir l'utiliser en exécutant des programmes réels et de pouvoir ainsi comparer les performances avec le logiciel

Architectures matérielles pour l'arithmétique stochastique discrète

PARIS-BIUSJ-Thèses (751052125) / SudocPARIS-BIUSJ-Mathématiques rech (751052111) / SudocSudocFranceF

RISC-V design using Free Open Source Software

International audienceThis tutorial aims to build a RISC-V processor using only free VLSI CAD tools with a symbolic technology approach (a refined Mead-Conway method as formerly used by MOSIS). The toolchain is currently organized as follow: A design description in VHDL language. Simulation with GHDL. Logical synthesis with Yosys. We use a frontend to convert VHDL into Verilog (from Alliance). Physical design (place & route) using Coriolis. DRC & LVS using Alliance. Timing analysis with Tas & Yagle. Symbolic to real translation (Alliance).Our first objective is to design a RISC-V for AMS 350nm node.The choice of symbolic technology is mainly made for three reasons: Node portability: From one symbolic layout, you may target multiple technologies. Community: Symbolic layout does not contain any NDA related information. As such it can freely be published and shared. Security.:With a published layout, everybody can check that the chip send back from the foundry is exactly what it should be (no hardware trojan)

Stratus : Un environnement de développement de circuits

NAT LIP6 CIANNational audienceno abstrac

Stratus : Un environnement de développement de circuits

NAT LIP6 CIANNational audienceno abstrac

MP-SoC Architecture for an Obstacle Detection Application in Pre-Crash Situation

International audienc

Novel architectural space exploration environment for multi-FPGA based prototyping systems

International audienc